Low power oscillator with charge subtraction scheme

摘要

An ultra-low power oscillator is designed for wake-up timers that can be used in compact wireless sensors, for example. A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators. This relaxes comparator design constraints, enabling low power operation. In 0.18 μm CMOS, the oscillator consumes 5.8 nW at room temperature with temperature stability of 45 ppm/° C. (−10° C. to 90° C.) and 1%/V line sensitivity.

主权项

1. A low power oscillator, comprising:
an integrating capacitor; a current source configured to charge the integrating capacitor; a subtraction circuit electrically coupled to the integrating capacitor and operable to subtract a fixed amount of charge from the integrating capacitor in response to a trigger signal, wherein the current source continues to charge the integrating capacitor while the subtraction circuit subtracts the fixed amount of charge from the integrating capacitor; and a first comparator configured to receive voltage across the integrating capacitor and compare the capacitor voltage to a first reference voltage, wherein the first comparator provides a trigger signal to the subtraction circuit when the integrating capacitor voltage exceeds the first reference voltage.