发明名称 PARITY CHECK SYSTEM
摘要 PURPOSE:To detect errors efficiently by loading a correct data to an ROM data register when scanning parity check operation is stopped once because of error detecting and then starting the operation again. CONSTITUTION:The titled system is provided with an ROM1 in which microprograms are stored, an ROM data register 2 in wich the micro-instructions are written, a parity check circuit 3, etc. The circuit 3 always executes the parity ckeck of an output of a circuit 2 and, when detecting a parity check error, the circuit 3 drives a control circuit 7 to stop a clock signal for loading. When a correct data which generates no parity error is loaded in the register 2, the output of the circuit 3 indicates no parity error, so that a circuit 7 outputs loading clocks again to the register 2 and the address register 6 to start scanning operation.
申请公布号 JPS57166652(A) 申请公布日期 1982.10.14
申请号 JP19810051140 申请日期 1981.04.07
申请人 TOKYO SHIBAURA DENKI KK 发明人 OONUKI TOSHIKIYO
分类号 G06F11/10 主分类号 G06F11/10
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