| 摘要 |
PURPOSE:To execute processing efficiently, automatically and continuously, by transferring a data to an optional number of memory areas dispersed in a storage device, by use of a processor, an address register and a continuous controlling circuit. CONSTITUTION:When a chain controlling circuit 12 requests a memory access to a processor 6, the processor 6 informs that it has released a memory access right, directly to a memory access DMA mechanism 20. Subsequently, the mechanism 20 opens a gate circuit 7, and sends contents of an address register 2 to a storage device 5 through an address bus 101. At the same time, the circuit 12 requests the device 5 to read out the stored contents. As a result, contents (k) of the head address of a memory area (a) of the device 5 are read out, and are inputted to an address register 1. Said contents (k) designate the head address of a memory area (b) to which a data is transferred next. In this way, is is started to transfer a data to an area B, and the data is transferred by being chained automatically. |
