| 摘要 |
A number of dividers for a non-integer divisor f, notably f=N-1/2. The divider comprises a chain of dynamic bistable elements, at least one of which is activated in reaction to the positive-going signal edges, while at least one is activated in reaction to the negative-going signal edges, having completely synchronous circuits and substantially synchronous circuits; a simple implementation for dividers with an arbitrary, and very large divider.
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