| 摘要 |
Logic analysers have groups of data acquisition sampling chips (10, 12, 14, 16) with a multiplicity of probe tips which are connected to the terminals of a product to be checked. According to the invention, the order in which the probe tips are connected can be disregarded since the correct ordering is carried out via the logic analyser (LA) itself. A permanently stored program enables the logic analyser to establish the correct order of the connections. The binary data from each group of data acquisition sampling chips (10, 12, 14, 16) are stored in a memory and can be converted into a hexadecimal form and stored in a display control device (48). A menu mode display which contains sampling channel identifiers can be displayed on the logic analyser (LA) display monitor (54) via a keypad (42). These identifiers reproduce the current order of the connections of the probe tips. A status table display of the binary (or hexadecimal) data can then be displayed on the logic analyser (LA) display monitor (54). If the probe tips have been attached to wrong terminals of the product to be checked, the keypad (42) is used for effecting the menu mode display. Using the keypad (42) and the logic analyser (LA) display monitor (54), the operator changes the order of the sampling channel identifiers on the display screen. This compensates for the incorrect order of the connections of the probe tips with the terminals. <IMAGE> |
