发明名称 TESTING DEVICE OF SEMICONDUCTOR MEMORY
摘要 PURPOSE:To make even a semiconductor memory containing defective bits useful, by collecting information that whether defective bits in the IC memory are admissible or not and information which minimize an address to be masked. CONSTITUTION:A fail bit map memory 8 performs accessings which are coincident with addresses of an IC memory to be tested 6, and stores defective bits information in a location assigned to defective bits in the memory 6. The bit information is transferred to a CPU1 after a series of tests is completed and displayed. Moreover, the total number of defective bits is counted by a fail bit counter 9 and the primary judgement on the conditions to be possessed by memories whose bits are partially defective, is performed. Then, computations which minimize the total sum of row lines and column lines containing defective bits are performed, and the secondary judgement whether the total sum of lines computated and selected is within an admissible range or not is made. When the memories whose bits are partially defective are within an admissible range, the result is available as mask to ascertain the quality of the memory 6, at the time of test to which the selected line follows as fail information.
申请公布号 JPS57164500(A) 申请公布日期 1982.10.09
申请号 JP19810049757 申请日期 1981.04.02
申请人 NIPPON DENKI KK 发明人 EGUCHI YASUO
分类号 G11C29/00;G01R31/28;G06F11/22;G11C29/04;G11C29/44 主分类号 G11C29/00
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