发明名称 SENSE BYTE PREFETCHING SYSTEM
摘要 PURPOSE:To increase the usage efficiency of an input and output controller, by issuing a sense command independently at an input and output channel device to an abnormal termination interruption of a command from a low-order device. CONSTITUTION:After an input and output channel device 2 connected to a CPU 1 receives a unit check transmitted from an input and output terminal 31 of an input and output controller 3, a sense command is returned to the terminal 21 and a sense byte transmitted from the device 3 is stored in a buffer 21. An operation system of the CPU 1 issues the sense command according to an abnormal interruption from the device 2 and fetches the sense byte from the device 2. Thus, the busy state is made less until the input and output controller receives the sense command and the usage efficiency can be increased.
申请公布号 JPS57164322(A) 申请公布日期 1982.10.08
申请号 JP19810048615 申请日期 1981.03.31
申请人 FUJITSU KK 发明人 MATSUSHIMA HITOSHI;KONDOU NORIHIKO
分类号 G06F13/00;G06F11/00;G06F13/12 主分类号 G06F13/00
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