| 摘要 |
PURPOSE:To prevent racing failure with simple constitution, by selectively connecting delay elements in parallel different from delay time to a signal transmission route between signal processing circuit groups. CONSTITUTION:A logical circuit C transferring signals is provided between input stage latch groups A0, A1.Ai and output stage latch groups B0, B1,...Bi. Delay elements DLAo-DLAi are connected in parallel with wirings lAo-lAi connecting the latch groups AO-Ai and the logical circuit C and the delay elements are selectively connected to the logical circuit C with selection gates GAo-GAi. Similarly, delay elements DLBo-DLBi are provided between the logical circuit C and the latch groups BO-Bi. In transferring a signal from the latch AO to the latch BO, if racing is produced on this route, the delay element DLAo or DLBo is in use with connection by the selection gate GAo or GBo. |
