| 摘要 |
PURPOSE:To reduce the storage capacity of gate pulse signal memory by storing various control signals through a signal synthesizer, a signal selector and a peak holding circuit in a digital memory. CONSTITUTION:Gate pulse signals h1-h6, i1-i6 generated to respective thyristors in one or more than two groups of thyristor groups formed of a plurality of thyristors are synthesized to one signal j1, j2 continued in time series manner in the respective groups, and either one of the gate pulse signals in the groups is selected in the group at every group via signal selectors 23, 24. The peak values of the output signals of respective signal synthesizers 21, 22 and the peak values of the output signals of the respective signal selectors are held at the sampling period of a digital memory in peak holding circuits 25-28, and the outputs are stored in a digital memory 30. |
