| 摘要 |
PURPOSE:To increase the width of hysteresis, by cascade connection of two stages of CMOS inverters and connecting a series circuit between an FET to which an input voltage is applied and an FET to which an output voltage is applied, in parallel with one FET of the first stage inverter. CONSTITUTION:An input signal VIN is applied to an inverter consisting of MOSFETs P1 and N1, and the output signal is applied to an inverter consisting of MOSFETs P4 and N2. The input voltage VIN is applied to the gate of a MOSFET P2 through a series circuit connection of MOSFETs P2 and P3 to the MOSFETP1, and an output voltage VOUT is applied to the gate of the MOSFETP3. When the input voltage VIN is at a low level, the output voltage VOUT is also at a low level, the MOSFETs P2 and P3 are conductive, the synthetic impedance of the MOSFETs P1, P2 and P3 is low and the threshold voltage when transition is made from low to high level, is increased. |
