| 摘要 |
PURPOSE:To improve the processing speed of the entitled controller by performing the simultaneous reading and erasing of data in a page buffer which stores character/pattern bit patterns. CONSTITUTION:A bit pattern data sent from a controlling part is set on a write data register 10 and stored in a page buffer 14 after passing through and AND gate 11 and an error check code (ECC) adding circuit 12 in which an ECC is added to the bit pattern data. At data reading, data are read out successively from the buffer 14 and, after ECC checking in an ECC checking circuit 15, outputted in a printing part. During the ECC checking period, a write signal is applied to the buffer 14, a data suppressing signal is made available and all outputs from the gate 11 are turned to (O). Thus, (O) is written in the locations specified by the address signal in the buffer 14, performing the simultaneous reading and erasing of data. |
