发明名称 Pulse frequency multiplier circuit
摘要 In a pulse frequency multiplying circuit, a first capacitor charged to a given potential is discharged through a first constant-current circuit during a period corresponding to a pulse width of a reference pulse. Then, the terminal voltage of the first capacitor is applied as a reference voltage to one input terminal of a comparator circuit. A triangle wave voltage formed by alternately discharging a pair of second capacitors charged to a given potential, through a second constant-current circuit with a current value n times that in the first constant-current circuit, is applied to the other input terminal of the comparator circuit. The output from the comparator circuit operates a flip-flop circuit. In accordance with the output signal, the charge/discharge operation of said second capacitors is switched, whereby said flip-flop circuit produces a pulse with a frequency n times that of the reference pulse.
申请公布号 US4353030(A) 申请公布日期 1982.10.05
申请号 US19800184312 申请日期 1980.09.05
申请人 HITACHI, LTD. 发明人 NAKAMURA, HIDEO;FUNABASHI, TSUNEO;KOIZUMI, HARUO
分类号 G06F7/68;H03K5/00;(IPC1-7):H03K5/00 主分类号 G06F7/68
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