| 摘要 |
PURPOSE:To enhance the detecting sensitivity, in a circuit wherein clock pulses whose frequency is higher than that of an input signal are counted and the interval between the signal inversions is detected, by using the N number of the clock pulses wherein the clock pulses are delayed at every 1/N of one clock cycle. CONSTITUTION:The clock CP is supplied directly to a counter 3D, to a counter 3C through a delay circuit 41, to a counter 3B through a delay circuit 42, and also to a counter 3A through a delay circuit 43. The amount of delay tau1 of the circuits 41-43 corresponds to tau0/N, where the number of counters is N, and tau0 is one cycle of the CP. The number of the clock pulses included in the time period of inversion of the input signal is counted in the counters 3D-3A by N, e.g. 4 clock pulses CPD-CPA which are formed in this way. The outputs of said counters 3D-3A are added and averaged. The voltage, which is converted in correspondence with the approximate average value is obtained across a capacitor 21, and the interval between the inversions of the input signals is detected. |
