发明名称 MEMORY ACCESS CONTROLLING SYSTEM
摘要 PURPOSE:To improve the precessing speed of a processor by applying only an address data and an address increment/decrement command to read/write continuous address data in a memory. CONSTITUTION:A read/write command R/W is applied from a processor to a memory controlling circuit 10 through a control bus 3 and an address a1 in a memory 11 is selected to read/write data. When the succeeding addresses (a2, a3...) are to be read/wirtten, the processor 1 outputs for example an address data A20 (not shown in the drawning) and an increment command U, and an address a20 is selected by the address data A20 to read/write the data. Then an AND circuit 5 in a control part 4 is opened, a counter 6 counts up +1 by a pulse signal C and the value is sent to an address decoder 9, selecting an address a21 (not shown in the figure) and executing the read/write operation. Since the pulse signal C is outputted in every read/write operation, the counter 6 adds numbers continuously and ascending addresses can be selected.
申请公布号 JPS57162182(A) 申请公布日期 1982.10.05
申请号 JP19810045115 申请日期 1981.03.27
申请人 FUJITSU KK 发明人 IURA AKIHIKO;YASUNAGA MASARU
分类号 G06F12/02;G11C8/04 主分类号 G06F12/02
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