| 摘要 |
PURPOSE:To design a transmitted signal generator easily at low cost, by using an ROM which outputs stored data by using as an address signal the output of a counter dividing the frequency of a transmission timing clock signal. CONSTITUTION:One frame of a transmitted signal has 90 bits and consists of a 13-bit all-0 frame synchronizing signal S, 55-bit transmitted data D, and a 22-bit CRC signal for error testing; and the data D and CRC signal have fixed bits F1-F6 of 1s for data testing at intervals of 13 bits. The 50-bit data D except the F1-F5 are inputted to a data selecting circuit DS1, and the 0 of the signal S, the 1s of the fixed bits F, and the output of the DS1 are used to generate 6 a CRC signal, which is inputted to SD2. A counter 3 divides the frequency of a transmission timing clock by 90 to output 7-bit data to ROMs 4 and 5 as an address signal. Then, 6-bit and 4-bit data which correspond to addresses are read out of ROMs 4 and 5 and inputted to the DS1 and DS2, so that a transmitted signal of desired frame constitution is outputted from the DS2. |
