发明名称 FAILURE PROCESSING SYSTEM
摘要 PURPOSE:To achieve early detection of bugs and efficient sytem operation, by setting either one mode of system control continuance or system control interruption in accordance with the types of a failure. CONSTITUTION:An FF6 determines the continuance of system control when an output is at (0) with the instruction of the software or the hardware and determines interruption when (1). When the output of the FF6 is at (0), if an error takes place, and AND gate 17 is at on-state and the selected output of a selection circuit 9 is tranmitted to a computer system via the gate 17. An AND gate 16 is also at on-state and a response signal from a register control circuit 8 is transmitted to a processor 2 via the gate 16. The device 2 analyzes the response signal and makes rewrite processing as required. On the other hand, when the output of FF6 is at (1), if an error takes place, the output of an NAND gate goes to (0), the gates 16 and 17 turn off, and the generation of the error can be recognized, because the device 2 has no response signal.
申请公布号 JPS57159353(A) 申请公布日期 1982.10.01
申请号 JP19810045815 申请日期 1981.03.28
申请人 FUJITSU KK 发明人 IIYAMA HIROSHI;USUI AKINORI;IBORI MITSUO
分类号 G06F11/00 主分类号 G06F11/00
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