| 摘要 |
PURPOSE:To pick up one output equivalent to an odd number at 50% duty cycle with simple constitution, by feeding back an output of a shift register to an exclusive logical sum circuit to which a clock signal is inputted. CONSTITUTION:Since an output Qn of a shift register 5 is at first at ''0'', an exclusive logical sum circuit EOR4 is at on-state and a clock signal A is an output B'. Since an inverter 6 outputs ''1'', an input terminal SI goes to ''1''. Thus, when a clock signal A0 is inputted to the EOR4 at a time T0, the ''1'' inputted to the input terminal SI is outputted to an output Q0 of the shift register 5 at the rise of the output signal B' of the EOR4. The clock signal advances the shift register. When the output Qn goes to ''1'', the input terminal SI goes to ''0'' and the output R0 goes to ''0'' at the rise of the output signal B' of the EOR4. |
