| 摘要 |
PURPOSE:To increase the accuracy of diagnosis with less additional circuit, by checking an address of a plurality of input and output channels at first connected to a bus with a little additional circuit. CONSTITUTION:When a command to read input and output channel address is incoming from a CPU2 with FFs 34, 44 and 54 reset, the command is interpreted with decoders 32, 42 and 52, and clocks CK1-CK3 are generated. While the clocks CK1-CK3 are zero, the states of the FFs 34, 44 and 54 are checked with gates 33, 43 and 53. If an output OE1 of a gate 22 of an input and output channel 3 goes to 1, the content of the input and output channel address of a switch 35 is outputted to a data line 25. The CPU2 reads the first input and output channel address outputted on the line 25. Then, a signal ENO1 goes to 1 with the leading of the clock CK1 and when an instruction of input and output channel address reading is incoming from the CPU2, the address of an input and output channel 4 is read. |
