发明名称 SYNCHRONIZING PATTERN GENERATING DEVICE
摘要 PURPOSE:To improve an error rate by using the combination of a minimum level and a maximum level only in an m(>2)-value recording as a synchronizing pattern. CONSTITUTION:A shift register 5 sends a synchronizing pattern where a minimum level is expressed as 0 and a maximum level is expressed as 1 in (m) levels. A switch 6 selects an output of a hold circuit 7 in M-bit representing the minimum level when the output of the register 5 is 0 and selects an output of a hold circuit 8 in M-bit representing the maximum level when the output of the register 5 is 1 and sends the result to an input 4. Thus, a synchronizing pattern of M-bit parallel comprising Ns-set of symbols consisting of the minimum level and the maximum level only among the (m) levels appears at the output of a selection circuit 1. Since the register 5 fetches a binary synchronizing patterns where the minimum level of the synchronizing pattern is expressed as 0 and the maximum pattern is expressed as 1 while the circuit 1 selects an input 2, a synchornizing pattern section always inserts the same pattern. The synchronizing pattern is generated by a simple circuit in this way and the error rate is improved.
申请公布号 JPS63122063(A) 申请公布日期 1988.05.26
申请号 JP19860269083 申请日期 1986.11.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IKETANI AKIRA
分类号 H04L7/08;G11B20/10 主分类号 H04L7/08
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