| 摘要 |
PURPOSE:To make it possible to read and write freely the contents of a channel memory unit by adding one control bit to each word in the channel control unit and then by controlling them by CPU. CONSTITUTION:When the contents of channel memory unit TSPM are rewritten by an instruction from CPU, gate circuits 10 and 13 are closed and circuit 11 and 14 are opened to write a combination of an information l bit and one control bit at an assigned address from CPU. The control bit at this time is set to ''0'' for write inhibition and its address is denoted by X. Write pulse generating circuit 17 is enable to generate a write pulse all the time on arrival of an instruction from CPU. Even if write operation would be done at address X by the indication of an address control circuit when normal switching operation is put into effect again, address X is read prior to the write operation and the control bit is held by latch circuit 16 for inhibiting the write operation. As a result, the contents of address X are unchangeable and even if address would be read by CPU, the previously-written contents never change. To return address X to normal operation, the write inhibition bit is only reset by the instruction of CPU. |
