| 摘要 |
PURPOSE:To prevent the abrupt change of the output voltage of an inverter by reducing the delay time by a time delay circuit to small value as the set voltage increases when it is transferred from a pulse width control to a full voltage state. CONSTITUTION:When the output voltage of a voltage amplifier 16 increases, a modulation pulse is eliminated, and only the rise of a wide width pulse is delayed by DELTAT by a stationary time delay circuit 8. The rise of the wide width pulse passed through a variable time delay circuit 8' does not have a delay (DELTAt= 0), but when both are synthesized by a logic circuit 18, the outputs of the respective AND gates are delayed by DELTAt only at the rising time of the wide width pulse. Since the delay time DELTAt is gradually reduced as the set voltage increases in this manner, the output voltage of the inverter increases as the DELTAt gradually reduces at v(T-DELTAt.n), and when DELTAt becomes zero, it becomes total voltage. Accordingly, the output voltage of the inverter is not abruptly varied. |
