Input stage for a monolithically integrated charge transfer device which generates two complementary charge packets

摘要

An input stage for a monolithically integrated charge transfer device of the type which generates two complementary charge packets from one input signal, said input stage having at least two transfer gates disposed between a source region in a semiconductor body and an input gate which is charged with the input signal. The two transfer gates in the input stage are connected to clock pulse voltages which operate at one half the clock frequency of the transfer stages covering the transfer channel of the charge transfer device. A particularly low-noise encoding of the input signal into the two complementary charge packets results thereby and the structure is particularly suitable for analog signal processing.