| 摘要 |
PURPOSE:To achieve easy and sure failure detection, by converting a periodical sequence operation of a central processing unit into an alternating signal through the use of a left and right shift register and commonly using a known failure detecting method. CONSTITUTION:Left shift pulses L1, L2-Ln of n sets, and n sets of right shift pulses R1, R2-Rn are outputted, and they are inputted to a left shift control circuit L and a right shift control circuit R incorporated to a left and right logical shift register 2 consisting of n+1-bit. An output from 0-bit (hereinafter SR0) output terminal of the shift register 2 and from n-bit (hereinafter SRn) output terminal is given to a failure output circuit 3. Further, a PS is a control circuit incorporated in the shift register 2 to initially set the full bits of the SR0-SRn of the shift register 2 to logical ''1''. |
