| 摘要 |
PURPOSE:To omit a register where the comparison result is stored for every bit, by comparing a synchronizing pattern and an internal pattern with each other in a comparing circuit and setting a JK FF and etc., which are reset at every monitor time start, by the disaccord output of comparison. CONSTITUTION:Data DATA1 from an internal pattern generating circuit PG and transmitted data DATA2 are compared with each other in a comparing circuit COMP. An FF FF1 is reset before the start of a frame monitor time (for example, 1 multiframe=4 frames) by a timing signal TM1. A timing signal TM3 synchronized with data DATA2 is applied as a clock to the FF FF1, and the FF FF1 is set when a synchronizing pattern F and an internal pattern P do not coincide with each other. The output of the FF FF1 is set to a synchronization protecting register REG2 by a timing signal TM2 of the end of the frame monitor time. |
