| 摘要 |
PURPOSE:To achieve demodulation while reducing the influences of noises by demodulating a binary signal during an N-fold zero-cross detection period, by selecting a counter which discriminates the binary signal, and another counter which resets said counter and then starts counting. CONSTITUTION:A received signal is amplified by a receiving amplifier 1 within a prescribed range, a BPF2 eliminate a signal of an opposed band and various noises, and a limiter 3 limits the saturation of amplitude. This amplitude-limited signal is inputted to a comparator 4 to output a digital value including FSK information in a period value, and the counter of a demodulating circuit 5 counts a fundamental clock during a zero-cross period to achieve digital demodulation. The counter selecting circuit of this circuit 5 consists of D-type FFs 6- 10, an exclusive OR gate 8, a 1/4 frequency dividing circuit 11, and AND gates 12-15, and outputs S1-S4, and reset signals R1-R4 are outputted synchronizing with a zero-cross synchronizing signal to demodulate binary signals during an N-fold zero-cross detection period. |
