| 摘要 |
PURPOSE:To reduce the number of components in use, by storing the same information to two sets of memories at the same time at write-in, in an arithmetic processor performing arithmetics among a lot of registers. CONSTITUTION:When an address selecting signal 18 goes to 0, information is respectively read out from one among 64 sets of storage positions under the designation of A field 1 and B field 2 in the 1st and 2nd memory devices 13 and 14, arithmetic is made at an ALU10, and the arithmetic result is outputted to a D bus 11. When the address selection signal changes to 1, the same location of the 64 sets of storage positions is selected to the memory devices 13 and 14 under the designation of a D field 3, and the information in a D bus 11 is written in the 1st and 2nd memory devices 13 and 14 at the same time with a write- in signal 15. Thus, since the hardware is less for the realization of an operation processor, the processor can be made small in size and high in the reliability. |
