| 摘要 |
In monolithically integrated MOS semiconductor memories, in particular dynamic MOS semiconductor memories, the gates of the switching transistors or switching memory transistors provided in the individual memory cells of the memory matrix are combined row by row by means of a word line WL assigned to the respective row of the memory matrix and addressed jointly via this word line. Since, in contrast to the bit lines of the memory matrix, these word lines WL are coupled exclusively capacitively to the semiconductor area of the memory matrix, the residual charges induced by the individual addressing operations cannot be discharged quickly enough, which can result in operational disruptions or a falsification of the information entered in the memory. Therefore, even in the case of known RAM memories of this type, measures have to be taken to ensure a rapid discharge of parasitic residual charges. The known circuits have the disadvantage, however, that they either also activate when word lines are in the addressed state and consequently result in disruptive impairment of the addressing signal in the word line concerned, or they do not fit very well into the layout of the memory matrix and consequently considerable efforts are necessary to accommodate them on the chip surface. These disadvantages are avoided if, according to the present invention, the series connection of two MOS field-effect transistors controlled simultaneously by the same signal voltage U1 are connected to the reference potential and, in addition, a switching point A, located between the two transistors, is connected via a third MOS transistor and via a further MOS transistor, connected as a resistor, to the other operating potential of the memory. <IMAGE> |
