| 摘要 |
PURPOSE:To accept with no waiting time an access request from a specific one of plural processors, by securing the synchronization between the memory cycle of a memory device and that of the specific processor. CONSTITUTION:A processor A10 which is required to accept an access request with no waiting time plus one or more processors B11 are connected to a memory device 1. The priority is previously set for each of the processors B11. The processor A10 is connected to the device 1 via paths 20, 21 and 22, and each of the processors B11 is connected to the device 1 via paths 23 and 24. A request acceptance control circuit 4 consists of a priority circuit 13, an AND gate 15 put between the output of the circuit 13 and a memory control circuit 3 plus a flip-flop 14 which controls the gate 15. |
