| 摘要 |
PURPOSE:To reduce a timing overhead, by arranging and controlling a counter circuit making the length of the shift register as the period and an access discriminating circuit, and controlling an address conversion circuit realizing a shift register equivalently through the use of RAMs. CONSTITUTION:An address generating circuit 2 is connected to a CPU1 to provide the function of a shift register equivalently and signals are inputted to an RAM3. A discriminating circuit 6 of the circuit 2 compares 13 an address signal 4 of the CPU 1 with a reference signal 12 of a preset register 11 to discriminate the truth or false of accessing to the shift register of the RAM3. The least and most significant addresses of the shift register are stored in registers 14 and 16 of a counter circuit 7 and the returning to the initial value is made by taking the length of the shift register as the period. A selection circuit 8 selects an address signal of the circuit 7 or an address signal 4 depending on the truth or false of the output of the circuit 6. Thus, the timing overhead during the execution of operation is reduced. |
