| 摘要 |
PURPOSE:To decrease the processing time of an instruction for a data processor, by suppressing the prefetching of such instruction that increases the increase of the processing time of instruction and prefetching only an instruction that is really effective. CONSTITUTION:When an instruction of an address 100 is over, an instruction executing part 1 feeds an address A102 to a main storage control part 2 and then requests the next instruction. The next instruction is fed immediately to the part 1 through a bus 33. On the other hand, a control part 2 sets the instruction executing time again to set it to an ETR27 and proceeds to the prefetch effect decision sequence. A suppression signal is delivered from a comparator 25 since the instruction executing time is shorter than the cycle time of the main storage device. Thus an instruction prefetch control circuit 28 suppresses the prefetching of an instruction and waits for the next instruction request which is given from the part 1. With the arrival of the next instruction, the part 2 reads the requested instruction by means of an address set at an SAR22. |
