发明名称 DIRECT MEMORY ACCESS CONTROLLING SYSTEM
摘要 PURPOSE:To realize the execution of a direct memory access substantially at any time without giving any effect to the working of a microprocessor unit at all, by monitoring the path effective signal which is delivered by a process unit prior to the transfer of data. CONSTITUTION:A microprocessor unit MPU, a memory M, an input/output device I/O, etc. are connected to a bus B. The unit MPU delivers a signal which shows the address of the transfer of data to an address path in the H level period in case the data is transferred via the bus B. Some signal usually exists in the address path, and an address path effective signal VMA valid memory address which shows that the signal of the existing address path is not a noise but an effective signal is set at an H level. This VMA signal is monitored to know whether it is an idle period or not. Then a direct memory access is carried out by making use of the idle period.
申请公布号 JPS57150018(A) 申请公布日期 1982.09.16
申请号 JP19810035097 申请日期 1981.03.11
申请人 FUJITSU KK 发明人 KUBOTA SHINICHI;SATOU AKIRA
分类号 G06F13/28 主分类号 G06F13/28
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