发明名称 Apparatus for digital demodulation or modulation of television chrominance signals
摘要 If an N.T.S.C. signal is to be demodulated using a line-locked sampling rate such as 800 times the line frequency, the ratio between the sampling period and the subcarrier period has the awkward value of 455/1600. Line-locked sampling is nevertheless desirable, e.g. in digital standards conversion. The subcarrier digital signals for digital demodulation are derived with the correct frequency from the sampling rate clock pulses CP by an adder and accumulator into which the number 582 is added modulo-2048 (the register is an 11-bit register) to generate an 11-bit number which represents the subcarrier phase angle at each sampling pulse and which addresses a ROM providing sin and cos values representing subcarrier samples. 582/2048 is not exactly equal to 455/1600 but 2048 is a desirable denominator as it is a power of 2 and implies a ROM of suitable size. <IMAGE> is exactly equal to 455/1600. Another adder and accumulator counts modulo-40960 by increments of 16384 and when this adder overflows, an extra 1 is added in through the carry-in to the first adder. Modulo 40960 is set up by altering 10256 to 40960 when the overflow occurs. Alternative numerical values are disclosed which apply to a PAL system with sampling rate 816 times line rate. Phase lock to the color burst is established by examination of the V output of the main demodulators during the color burst. V=sine theta where theta is the phase error. This quantity is applied via a negative feedback loop to effect fine adjustment of the numbers 40960 and 16384. Similar provisions for PAL are disclosed as is the generation of a PAL switch signal of the correct phase. The apparatus can also be employed as a modulator.
申请公布号 US4349833(A) 申请公布日期 1982.09.14
申请号 US19800185069 申请日期 1980.09.08
申请人 BRITISH BROADCASTING CORPORATION 发明人 CLARKE, CHRISTOPHER K. P.
分类号 H04N11/04;H04N11/16;(IPC1-7):H04N9/53 主分类号 H04N11/04
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