Digital-to-analog converter with improved compensation arrangement for offset voltage variations

摘要

A digital-to-analog converter comprising a plurality of identical transistor current sources with their emitters connected to respective shunt legs of an R-2R ladder network for establishing binary weighting of the transistor currents. The effects of variations in transistor offset voltage are compensated for by returning the ladder termination resistor to a voltage which is 2(kT/q)1n 2 more positive than the last active stage of the converter.