发明名称 DATA PROCESSOR
摘要 PURPOSE:To achieve a data processor in which input/output of information is performed in byte unit and the internal processing is processed in a form that redundancy bits are deleted in non-byte-unit, by providing a deletion circuit and an insertion circuit for the redundancy bits. CONSTITUTION:Input information P' is given in the form of 2-byte added with redundancy bits at a hatch section to fields B, C and D, the redundancy bits are deleted with a redundancy bit deletion circuit 12 in a data processor 10 and stored to a memory 13 as information Q' in a form in non-byte unit and subject to internal operations such as transfer and operation. In outputting the information to the outside of the data processor 10, the output information Q' is given to a redundancy bit insertion circuit 14, where the redundancy bits are added and converted into information R' in the same two-byte as at input. Thus, the capacity of the memory 13 in the data processor and that of other internal circuits can be reduced.
申请公布号 JPS57146341(A) 申请公布日期 1982.09.09
申请号 JP19810029872 申请日期 1981.03.04
申请人 HITACHI SEISAKUSHO KK 发明人 SATOU YOSHIO;OGAWA TETSUJI
分类号 G06F5/00 主分类号 G06F5/00
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