发明名称 DATA PROCESSING DEVICE
摘要 PURPOSE:To increase a substantial machine cycle with less amount of hardware, by reducing a waiting time through the difference of confirming timing of branch conditions, in a data processor of a microprogramming control system. CONSTITUTION:A timing control circuit 10 controls an operating timing of each device, and three phase fundamental clocks T0, T1 and T2 and a dummy clock TX are outputted. When branching is confirmed for establishment/unestablishment before a point A, one machine cycle is finished with three clocks of T0, T1, and T2 (S type machine cycle 11), and when not confirmed before the pint A but confirmed at a point B, one machine cycle is finished with 4 clocks of T0, T1, T2 and T3 (L type machine cycle 12). The both machine cycles are determined with a value of a conditional branching field 5, and when the circuit 10 takes the L type machine cycle, the clock TX is inserted after the clock T1 to give a delay to the generation of the T2.
申请公布号 JPS57146347(A) 申请公布日期 1982.09.09
申请号 JP19810031312 申请日期 1981.03.06
申请人 HITACHI SEISAKUSHO KK 发明人 FUJIOKA YOSHINORI
分类号 G06F9/22;G06F9/26;G06F9/32 主分类号 G06F9/22
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