| 摘要 |
PURPOSE:To prevent an increase in the number of parts even when a sampling period is shortened and delay is increased, by delaying an input pulse signal by a time which depends upon the sampling period of a clock oscillator and the number of addresses of an RAM. CONSTITUTION:When address information is sent from an address generating circuit 4 to an RAM7, a readout timing generating circuit 3 operates and the RAM7 is placed in a readable state. Then, a driving timing generating circuit 2 for an output holding circuit which drives the output holding circuit 8 operates and the contents in the address of the RAM7 specified by the address generating circuit 4 are sent to an output terminal through the output holding circuit 8. Then, a writing timing generating circuit 5 which holds the RAM7 in readiness for writing operates and the RAM7 is placed in a writable state. Then, a driving timing generating circuit 6 which drives an input gate circuit 10 operates to write a pulse signal applied to an input terminal 11 in the RAM7. |
