| 摘要 |
This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two-bit decoder for receiving each like order pairs of digits Ai, Bi of two n digit binary numbers A0, A1 . . . An-1 and B0, B1 . . . Bn-1 plus a carry Cin. The decoders generate an output signal called a minterm on a different line for each of the four possible combinations AixBi, AixBi, AixBi and AixBi of the true and complement of each pair. The minterms from the decoders are fed to an array called the product term generator or AND array which generates product terms fp=f0(A0,B0)xf1(A1,B1)x . . . xfn-1(An-1,Bn-1)xfn(Cin) The product terms are fed to a second array called a sums of product terms generator or OR array that sums product terms fp. A series of latches is last in the sequence of logic elements making up the PLA. These latches each perform an Exclusive-OR function to generate a sum bit Si that is an Exclusive-OR of two functions supplied by the OR array to the inputs of the latches to generate a sum S0, S1 . . . Sn-1 plus a carry Cout for the adder at the output of the PLA. The adder is optimized for a PLA with latches that perform an Exclusive-OR function and is more efficient than known adders embodied in PLAs, in which the output latches perform an AND function.
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