| 摘要 |
A buffer circuit operable with high speed is disclosed. The circuit comprises an input node, an amplifying means having an input coupled to the input node, a first power source, a second power source, a first transistor coupled between the first potential source and the input node, a second transistor coupled between the input node and the second power source, and means responsive to the output of the amplifying means for respectively providing a first signal and a second signal complementary to the first signal to the gates of the first and second transistors so as to restrict a potential amplitude at the input mode.
|
