| 摘要 |
PURPOSE:To simplify the circuit, by using an addition gate, whose input contains 5 or 0, as a single gate for + or -quinary without dividing this gata into a gate for addition and a gate for subtraction. CONSTITUTION:Numeric values equal to each other of augends A (5-0) and addends B (5-0) are inputted to OR gates R respectively, and their outputs are queued to generate a half martix. An AND gate to which two matrix lines are inputted is marked with a small circle at each intersection. Since 5 or 0 is inputted to the gate marked with a single circle M, the output is inputted to a numeric output gate A' of the preceding stage as it is. Two gates WS and WD are provided at the intersection marked with a double circle W, and a signal S of ASBS=11 or 00 (AS and BS are signs of A and B) is connected to the gate WS, and its NOT signal is connected to the gate WD. The gate marked with a triple circle is constituted as shown in the right of figure 2, and the WS is divided into a gate WS1 for A+B and a gate WS2 for A-B, and an NOT signal of ASBS=10 and 01 is connected to the gate WS1, and the gate WS1 is operated for ASBS=11 or 00. |
