| 摘要 |
PURPOSE:To speed up the interpretation of instruction, by starting the interprepation of the next instruction at the cycle when the final operand is in a register direct mode is detected. CONSTITUTION:The operation code of an instruction is outputted from an instruction buffer 401 through a data aligner 403, and the content an ROM404 is read out by taking this output as an address. Next, the output of the aligner 403 is applied to a decoder 406 to decode the modifier of the 1st operand. As a result, if a displacement section exists, this is transmitted to an addess calculation unit 310. A flag FLG408 is set with the output of the ROM404. The content of an instruction decoder address register 413 is set to an address where the modifier of the 2nd operand exists. The output of the aligner 403 is applied to a decoder 405 to detect if the 2nd operand is in register direct mode, and if so, the interpretation of the next instruction is started with the said cycle. |
