| 摘要 |
PURPOSE:To obtain a highly integrated and low power comsuming memory cell for the subject device by a method wherein impurities are doubly introduced in the capacitance element section on the surface of a semiconductor, the P-N junction capacitance is added to the capacitance located among a substrate, a reverse conductive type layer and an electrode, and then the substrate is biased. CONSTITUTION:A P layer 102 and an oxide thick film 103, which will be adjoining the layer 102, are selectively provided on a P type Si substrate 101, and a resist mask 105 is provided on a gate insulating film 104. A P<+> layer 106 and an N layer 107 are formed by double implanting B and P ions of the prescribed density, electrodes 104 and 109 are selectively provided, and they are opposed each other. Then, N layers 110 and 111 are formed by heat-diffusing P. Then, the above is covered by a PSG112, an aperture is provided on the N layer 111, an Al wiring 113 is led out, and a biasing electrode 114 is attached on the reverse side of the substrate 101. According to this constitution, as the P-N junction capacitance of both the N layer 107 and the electrode 114 is longitudinal formed in parallel to the capacitance located between the electrode 108 and the N layer 107, the occupation area is made smaller, thereby enabling to reduce the power consumption and to perform a high-speed operation by applying a substrate bias. |
