发明名称 DATA PROCESSOR
摘要 PURPOSE:To use a hardware effectively without stopping the execution of a microinstruction, by providing an instruction stopping the execution of the microinstruction until the reception is made after checking if a request is received. CONSTITUTION:When an output signal 22 of a readout register 5 is inputted to a decoder 6 and a request instruction 24 to a main storage control device 2 goes to logically 1, a request signal 27 of logical 1 is outputted to a main storage controller 2 from a request reception control circuit 8. This signal 27 goes logical 0 when a request reception signal 28 is made effective. Further, an instruction 25 which checks if the request is received goes to logical 1. The signal 25 generates a request synchronizing signal 31 of ligical 1. The status of the request signal 28 and the request reception signal is checked in response to the signal 31 and if the signal 28 is not made effective, a signal 33 stopping the execution of the microinstruction is made to logical 1. Thus, an address register 7 and renewal signals 35 and 36 of the register 5 go to logical 0 and the execution of the microinstruction is stopped.
申请公布号 JPS57141757(A) 申请公布日期 1982.09.02
申请号 JP19810027515 申请日期 1981.02.26
申请人 NIPPON DENKI KK 发明人 KAMATA YOSHIROU
分类号 G06F9/22;G06F9/26;G06F9/34;G06F9/38 主分类号 G06F9/22
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