| 摘要 |
<p>A digital processing circuit for effecting a multiplication operation is disclosed which converts a multiplier into coefficients according to Booth's algorithm, forms partial products of said coefficients with the multiplicand, and forms ihe final multiplication result by summing up the partial products in an adding means, the partial products being successively fed to a first input of said adding means and the output of said adding means being recirculated in a loop to a second input of said adding means. The invention results is a substantial simplification of the hardware by eliminating the necessity of having a plurality of a partial product producing circuits and adder circuits. Time control and matching with a processing system are easy, and the invention is particularly suited for use in a digital filter or the like, especially in speach processing.</p> |
