| 摘要 |
In a central timer unit (CTU), incoming stochastically occurring control information, for example dial pulse data, which is to be buffered for execution after individually assigned delay times, is stored in a random access memory (RAM). Address linkage information is written into the RAM, with each piece of received control data, and chains the incoming data to other received data which is to be read from the RAM at the same absolute (real) time. Each piece of control data is automatically retrieved from the RAM, and retransmitted elsewhere in the telecommunications system, after its specified and predetermined buffering time in the CTU. The pieces of buffered data are individually linked to the CTU's internal time base, which is developed by a clock generator coupled to ring counter driven, hierarchially arranged, time control units. Each of these sequentially arranged timer units also includes memory elements for storing the RAM addresses of buffered data items which will time-out in a particular cyclic period associated with that particular timer unit. The CTU further includes an internal control device, having an adder unit, which determines execution times for incoming data by combining delay time values and internal storage times. Bi-directional address linking is also taught, thereby facilitating cancellation of void pieces of buffered data, prior to their respective execution times, without disturbing non-cancelled data.
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