| 摘要 |
A package for interconnecting a plurality of integrated circuit chips including a dielectric body having a plurality of intersecting planes and a plurality of metallized interconnection patterns located thereon. Conductive interconnecting lines connected to at least some of said metallized patterns located on different intersecting planes provide inter-plane electrical continuity, and input/output connectors connect to at least one of the metallized patterns for connecting to the outside world. |
