Circuit arrangement for establishing phase synchronism between clock pulses and sync bits of data envelopes

摘要

Circuit arrangement for establishing phase synchronism between clock pulses (T10) and sync bits (S) of data envelopes (EV1, EV2) which in each case contain n bits and are transmitted within the framework of a data signal (D10). The data signal (D10) is delayed by a number of cells of a shift register (SR) and forwarded via a switch (SW) to a comparator which compares bits which are n bits apart from one another with one another and transmits comparison signals (V1) or (V2) which signal defective or, where appropriate, identified synchronisation. A first counter (Z1) counts the comparison signals (V1) relating to the defective synchronisation and, once a predefined counter reading is reached, transmits an error signal (F) to a second counter, which controls the switch (SW) according to its counter readings. <IMAGE>