Non-volatile semiconductor memory circuits.

摘要

A non-volatile semiconductor memory circuit having at least one variable threshold FATMOS transistor (Q3, Q4) in the cross-coupled lateral branches and a plurality of input switching transistors controlling operation of the circuit. Capacitive imbalance between the nodes (X1, X2) of the circuit between a node (X1) and an input switching transistor (Q14) driven by the same control signal as a corresponding transistor (Q13) connected between the other node (X2) and an input switching transistor (Q15). This reduces the occurrence of wrong-state switching in the circuit during reading.