| 摘要 |
The system converts linearly coded digital signals into non- linearly coded digital signals with a multiple segment characteristic. It aligns the signal values for the two different codes using two stores (K1,K2) and an NOR logic (N). A number of successive higher value bits (2to powers 5 to 13) of the linear coded signal values are used as address signals for one stores (A1) for characterising the characteristic segments, the lower value bits (2 to powers 2 to 14) excepting the lowest bit (2 to power 0) used as address signals for the second store (K2) to address stored digital words. These lower value bits (1 (2 to powers 1 to 4) are also fed to the NOR logic (N), its output fed to the first store (K1). The second store (K2) has remaining address inputs (A9 to A4) receiving the highest value bit (2 to power 13) and the lower bit value outputs (07 to 05) of the first store (A1) its outputs (01 to 04) and the higher value outputs (06..08) of the first store, forming the converted information (SDK). |
