| 摘要 |
PURPOSE:To decrease the number of address comparators by changing control systems for a store buffer. CONSTITUTION:For fetching data from a main storage unit 1, when the bit 25 of a fetch address (FA) is a[1], eight addresses of a line address stack 7-0 are read and compared by an address comparator 12 with the bits 21-24 of the FA. Every time data is written in a bank 6-0, the counter value of an input point 10-0 goes up by one, and similarly every time data is written in a bank 6-1, the count value of a 10-1 goes up by one. When data is read out of a store buffer (STB), a priority level circuit 13 controls a selector SEL so that data stored in the STB earlier is outputted earlier. |
