| 摘要 |
PURPOSE:To obtain a mode with short cycle time, by shortening cycle time required for a write cycle in successive modes. CONSTITUTION:When a row address latch means (-RAS) is activated, a buffer 11 and a row decoder 1 operate and information from a memory cell 22 connected to a word line is transmitted to a bit line 21. For writing infromation in the memory cell 22 in successive modes, the -RAS latches pieces of information to be written in the memory cell. Those latched pieces of information are written in the cell 22 simultaneously or successively through individual I/O lines 5. Therefore, it is confirmed that pieces informations are being written in >=2 different addresses simultaneously. |
